1. Field of the Invention
The invention relates to a sample-and-hold amplification circuit, and more particularly to a sample-and-hold amplification circuit which simultaneously perform sampling and holding operations.
2. Description of the Related Art
FIG. 1 shows a conventional sample-and-hold amplification circuit. As shown in FIG. 1, a sample-and-hold amplification circuit 1 comprises an amplifier 10, pass switches A1-A6 and B1-B4, and capacitors C1-C4. The pass switches A1-A3 and B1-B2 and the capacitors C1-C2 form sample-and-hold unit 11. The pass switches A4-A6 and B3-B4 and the capacitors C3-C4 form sample-and-hold unit 12. The pass switches A1-A6 are turned on according to a sample clock signal CL11, while the pass switches B1-B4 are turned on according to a hold clock signal CL12. The sample clock signal CL11 is inverse to the hold clock signal CL12.
When the sample clock signal CL11 is active, the pass switches A1-A6 are turned on while the pass switches B1-B4 are turned off, and positive input voltage Vip and negative input voltage Vin are respectively stored into capacitors C1 and C3, such that both of the sample-and-hold units 11 and 12 perform sampling operations. When the hold clock signal CL12 is active, the pass switches A1-A6 are turned off while the pass switches B1-B4 are turned on, and the stored positive input voltage Vip and negative input voltage stored Vin are coupled into the amplifier 10, such that both of the sample-and-hold units 11 and 12 perform holding operations. The amplifier 10 thus generates output voltage signals. Each sample-and-hold unit performs the sampling or holding operation once, in other words, the sampling and holding operations are not performed simultaneously by this architecture.